The present disclosure relates to a filter circuit and, more particularly, to a loop filter used in a phase-locked loop (PLL) circuit and a loop filtering method for a PLL circuit.
A PLL circuit, one of fundamental parts of a communication system, is a feedback system that maintains a constant phase difference between an output signal and a reference signal. For example, transceivers in wireless communication systems utilize PLL circuits for frequency synthesis, and clock and data recovery (CDR). Also, PLL circuits are incorporated into almost all high speed mixed-signal system-on-chips (SoCs) for clock synchronization, frequency demodulation and frequency synthesis. An SoC is an integrated circuit which integrates numerous components into a single chip to contain various functions such as digital, analog, mixed-signal and radio-frequency (RF) functions.